The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Increasingly, public and private communications networks are being built and expanded using various packet technologies, such as Internet Protocol (IP).
A network device, such as a switch or router, typically receives, processes, and forwards or discards a packet based on one or more criteria, including the type of protocol used by the packet, addresses of the packet (e.g., source, destination, group), and type or quality of service requested. Additionally, one or more security operations are typically performed on each packet.
Known packet processes typically have architectures consisting of a pipeline with fixed stages of hardware resource blocks and micro-sequencers. The hardware resource blocks include functionality like parsing of packet headers based on register based configuration for packet classification and longest prefix match search. The micro-sequencers can do header modification based on results from resource blocks. This architecture strikes a balance between high performance (similar to levels of completely hardwired packet processors) and flexibility. There have been numerous tweaks made to the micro-code to support features not understood when the original ASICs were designed that would have required a re-spin if the micro-sequencers had not be included.
The primary difficulty with this architecture is that the pipeline architecture still assumes that the ordering of processing and resource accesses is mostly understood at the time of the application-specific integrated circuit (ASIC) design, and is fairly consistent across all applications. If new applications want to use resources (e.g., memories, lookup engines, or content-addressable memories) in new ways or want to more flexibly trade-off performance and features, the pipeline architecture is rigid. Additionally, the complexity of programming the pipelined engines greatly escalates with an increased number of processor stages. Also, the split packet processing functionality across the various stages of the pipelined architecture greatly constrains the packet processing capabilities. Needed are new methods and apparatus for processing packets.